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ADSP-2104 - Low Cost DSP Microcomputers

Download the ADSP-2104 datasheet PDF. This datasheet also covers the ADSP2104 variant, as both devices belong to the same low cost dsp microcomputers family and are provided as variant models within a single manufacturer datasheet.

General Description

Low Cost DSP Microcomputers ADSP-2104/ADSP-2109 FUNCTIONAL BLOCK DIAGRAM DATA ADDRESS GENERATORS DAG 1 DAG 2 MEMORY PROGRAM SEQUENCER PROGRAM MEMORY DATA MEMORY EXTERNAL ADDRESS BUS PROGRAM MEMORY ADDRESS DATA MEMORY ADDRESS PROGRAM MEMORY DATA DATA MEMORY DATA EXTERNAL DATA BUS ARITHMETIC UNITS

Key Features

  • 20 MIPS, 50 ns Maximum Instruction Rate Separate On-Chip Buses for Program and Data Memory Program Memory Stores Both Instructions and Data (Three-Bus Performance) Dual Data Address Generators with Modulo and Bit-Reverse Addressing Efficient Program Sequencing with Zero-Overhead Looping: Single-Cycle Loop Setup Automatic Booting of On-Chip Program Memory from Byte-Wide External Memory (e. g. , EPROM ) Double-Buffered Serial Ports with Companding Hardware, Automatic Data Buffering, and Multichannel.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (ADSP2104_AnalogDevices.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

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Other Datasheets by Analog Devices

Part Number Description
ADSP-2100A DSP Microcomputers
ADSP-2101 DSP Microcomputers
ADSP-21020 32/40-Bit IEEE Floating-Point DSP Microprocessor
ADSP-2103 DSP Microcomputers
ADSP-2105 DSP Microcomputers

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
a SUMMARY 16-Bit Fixed-Point DSP Microprocessors with On-Chip Memory Enhanced Harvard Architecture for Three-Bus Performance: Instruction Bus & Dual Data Buses Independent Computation Units: ALU, Multiplier/ Accumulator, and Shifter Single-Cycle Instruction Execution & Multifunction Instructions On-Chip Program Memory RAM or ROM & Data Memory RAM Integrated I/O Peripherals: Serial Ports and Timer FEATURES 20 MIPS, 50 ns Maximum Instruction Rate Separate On-Chip Buses for Program and Data Memory Program Memory Stores Both Instructions and Data (Three-Bus Performance) Dual Data Address Generators with Modulo and Bit-Reverse Addressing Efficient Program Sequencing with Zero-Overhead Looping: Single-Cycle Loop Setup Automatic Booting of On-Chip Program Memory from Byte-Wide External Memory (e.