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ADSP-21367 - SHARC Processor

This page provides the datasheet information for the ADSP-21367, a member of the ADSP-2136 SHARC Processor family.

Description

3 SHARC Family Core Architecture 4 Family Peripheral Architecture 7 I/O Processor

Features

  • include JTAG access to memory permitted with a 64-bit key Protected memory regions that can be assigned to limit access under program control to sensitive code PLL has a wide variety of software and hardware multi- plier/divider ratios Available in 256-ball BGA_ED and 208-lead LQFP_EP packages SIMD Core Instruction Cache 5 stage Sequencer DAG1/2 Timer PEx PEy FLAGx/IRQx/ TMREXP JTAG Block 0 RAM/ROM Internal Memory Block 1 RAM/ROM Block 2 RAM Block 3 RAM DMD 64-BIT S DMD 64-BIT P.

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Datasheet preview – ADSP-21367

Datasheet Details

Part number ADSP-21367
Manufacturer Analog Devices
File Size 1.50 MB
Description SHARC Processor
Datasheet download datasheet ADSP-21367 Datasheet
Additional preview pages of the ADSP-21367 datasheet.
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Full PDF Text Transcription

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SHARC Processor ADSP-21367/ADSP-21368/ADSP-21369 SUMMARY High performance 32-bit/40-bit floating-point processor optimized for high performance audio processing Single-instruction, multiple-data (SIMD) computational architecture On-chip memory—2M bits of on-chip SRAM and 6M bits of on-chip mask programmable ROM Code compatible with all other members of the SHARC family The ADSP-21367/ADSP-21368/ADSP-21369 are available with a 400 MHz core instruction rate with unique audiocentric peripherals such as the digital applications interface, S/PDIF transceiver, serial ports, 8-channel asynchronous sample rate converter, precision clock generators, and more. For complete ordering information, see Ordering Guide on Page 61.
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