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ADSP-21564 - SHARC+ Single Core High Performance DSP

This page provides the datasheet information for the ADSP-21564, a member of the ADSP-21560 SHARC+ Single Core High Performance DSP family.

Description

3 SHARC Processor 4 SHARC+ Core Architecture 6 System Infrastructure 8 System Memory Map 8 Security

Features

  • Enhanced SHARC+ high performance floating-point core Up to 933 MHz 5 Mb (640 kB) Level 1 (L1) SRAM memory with parity (optional ability to configure as cache) 32-bit, 40-bit, and 64-bit floating-point support 32-bit fixed point Byte, short word, word, long word addressed Powerful DMA system On-chip memory protection Integrated safety features 17 mm × 17 mm, 400-ball CSP_BGA (0.8 mm pitch), RoHS compliant 120-lead LQFP_EP (0.4 mm pitch), RoHS compliant Low system power across automotive temperatu.

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Datasheet preview – ADSP-21564

Datasheet Details

Part number ADSP-21564
Manufacturer Analog Devices
File Size 2.57 MB
Description SHARC+ Single Core High Performance DSP
Datasheet download datasheet ADSP-21564 Datasheet
Additional preview pages of the ADSP-21564 datasheet.

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Full PDF Text Transcription

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SHARC+ Single Core High Performance DSP (Up to 933 MHz) Preliminary Technical Data SYSTEM FEATURES Enhanced SHARC+ high performance floating-point core Up to 933 MHz 5 Mb (640 kB) Level 1 (L1) SRAM memory with parity (optional ability to configure as cache) 32-bit, 40-bit, and 64-bit floating-point support 32-bit fixed point Byte, short word, word, long word addressed Powerful DMA system On-chip memory protection Integrated safety features 17 mm × 17 mm, 400-ball CSP_BGA (0.8 mm pitch), RoHS compliant 120-lead LQFP_EP (0.4 mm pitch), RoHS compliant Low system power across automotive temperature range 3.
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