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DSP Microcomputer
ADSP-2171/ADSP-2172/ADSP-2173
FEATURES 30 ns Instruction Cycle Time (33 MIPS) from
16.67 MHz Crystal at 5.0 V 50 ns Instruction Cycle Time (20 MIPS) from 10 MHz
Crystal at 3.3 V ADSP-2100 Family Code & Function Compatible with
New Instruction Set Enhancements for Bit Manipulation Instructions, Multiplication Instructions, Biased Rounding, and Global Interrupt Masking Bus Grant Hang Logic 2K Words of On-Chip Program Memory RAM 2K Words of On-Chip Data Memory RAM 8K Words of On-Chip Program Memory ROM (ADSP-2172) 8- or 16-Bit Parallel Host Interface Port 300 mW Typical Power Dissipation at 5.0 V at 30 ns 70 mW Typical Power Dissipation at 3.3 V at 50 ns Powerdown Mode Featuring Less than 0.55 mW (ADSP2171/ADSP-2172) or 0.
ADSP-2173 Datasheet
