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ADSP-CM419F - Mixed-Signal Dual-Core Control Processor

This page provides the datasheet information for the ADSP-CM419F, a member of the ADSP-CM411F Mixed-Signal Dual-Core Control Processor family.

Description

3 Analog Front End 4 Dual-Core System Architecture 10 EmbeddedICE 13 Processor Infrastructure 13 Memory Architecture 17 System Acceleration 19 Security

Features

  • Up to 240 MHz ARM Cortex-M4 with floating-point unit with up to 160K Byte zero-wait-state ECC SRAM Safety based dual independent- core concept Up to 1M Byte high performance ECC FLASH that can execute instructions at near SRAM speed Highest precision, low latency 31-channel analog front end 100 MHz ARM Cortex-M0 supervisor core with 32K Byte zero wait state ECC SRAM Single 3.3 V power supply Static memory controller (SMC) with asynchronous memory interface that supports 8-bit and 16-bit memories.

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Datasheet preview – ADSP-CM419F

Datasheet Details

Part number ADSP-CM419F
Manufacturer Analog Devices
File Size 2.45 MB
Description Mixed-Signal Dual-Core Control Processor
Datasheet download datasheet ADSP-CM419F Datasheet
Additional preview pages of the ADSP-CM419F datasheet.

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Full PDF Text Transcription

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Mixed-Signal Dual-Core Control Processor with ARM Cortex-M4/M0 and 16-bit ADCs Preliminary Technical Data ADSP-CM411F/412F/413F/416F/417F/418F/419F SYSTEM FEATURES Up to 240 MHz ARM Cortex-M4 with floating-point unit with up to 160K Byte zero-wait-state ECC SRAM Safety based dual independent- core concept Up to 1M Byte high performance ECC FLASH that can execute instructions at near SRAM speed Highest precision, low latency 31-channel analog front end 100 MHz ARM Cortex-M0 supervisor core with 32K Byte zero wait state ECC SRAM Single 3.
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