HMC7044 Overview
44 fs typical (12 kHz to 20 MHz) at 2457.6 MHz Noise floor: −156 dBc/Hz at 2457.6 MHz Low phase noise:.
HMC7044 Key Features
- Ultralow rms jitter: 44 fs typical (12 kHz to 20 MHz) at 2457.6 MHz
- Noise floor: -156 dBc/Hz at 2457.6 MHz
- Low phase noise: -141.7 dBc/Hz at 800 kHz, 983.04 MHz output
- Up to 14 LVDS, LVPECL, or CML type device clocks (DCLKs)
- Maximum CLKOUTx/CLKOUTx and SCLKOUTx/SCLKOUTx
- JESD204B- and JESD204C-patible system reference (SYS
- 25 ps analog, and ½ VCO cycle digital delay independently
- SYSREF valid interrupt to simplify JESD204B and JESD204C
- Narrow-band, dual core VCOs
- Up to 2 buffered voltage controlled oscillator (VCXO) outputs