Datasheet4U Logo Datasheet4U.com

S19235 - 16-Bit Transceiver

This page provides the datasheet information for the S19235, a member of the S19235PB11 16-Bit Transceiver family.

Description

The S19235 SONET/SDH/FEC and 10 Gigabit Ethernet (GbE) transceiver is one of the latest additions to AMCC’s SuperPHYTM product family.

The S19235 device provides fully integrated serialization/de-serialization capabilities for low power Intermediate and long Reach OC-192 applications.

Features

  • Operational from 9.953 Gbps to 11.1 Gbps.
  • Low Power (1100 mW Typical).
  • 1.2 V and 1.8/2.5/3.3 V Power Supply.
  • Built-In Self Test (BIST) Feature with error counter.
  • On-chip High-Frequency PLL for Clock Generation and Clock Recovery.
  • 16-bit LVDS Parallel Data Path.
  • TX and RX Lock Detect Indication.
  • Serial and Reference Loop Timing Modes.
  • Line and Diagnostic Loopback Mode for Faulty Node Identification.
  • Operat.

📥 Download Datasheet

Datasheet preview – S19235

Datasheet Details

Part number S19235
Manufacturer Applied Micro Circuits
File Size 141.14 KB
Description 16-Bit Transceiver
Datasheet download datasheet S19235 Datasheet
Additional preview pages of the S19235 datasheet.

📁 Similar Datasheet

  • S19233 - 10 GbE/Fibre Channel/SONET/SDH/FEC Dual CDR (AMCC)
  • S19 - SURFACE MOUNT SCHOTTKY BARRIER RECTIFIER (YS)
  • S190GC-1AS - Yellow Green LED (Luckylight)
  • S190PGC-2A - 0603 Package Yellow Green Chip LED (Luckylight)
  • S190PGC-G5-1BS - Pure Green LED (Luckylight)
  • S1954 - NPN Transistor (Toshiba)
  • S1955 - Silicon PNP Transistor (Toshiba)
  • S19A100N - Monitor User Manual (Samsung)
Other Datasheets by Applied Micro Circuits

Full PDF Text Transcription

Click to expand full text
( DataSheet : www.DataSheet4U.com ) S19235 OC-192 SONET/SDH/FEC/GbE 16-bit Transceiver and the serial receive interface. The system timing circuitry consists of a highspeed phase detector, clock dividers, and clock distribution. The device utilizes on-chip clock synthesis PLL components that allow the use of a slower external clock reference, 155.52 MHz or 622.08 MHz (or equivalent FEC/10GbE rate), in support of existing system clocking schemes. The low-jitter, 16-bit, Low Voltage Differential Signaling (LVDS) interfaces guarantee compliance with the bit-error rate requirements of the Telecordia and ITU-T standards.
Published: |