AT91SAM9263 Datasheet PDF

FEATURES

● Incorporates the ARM926EJ-S™ ARM® Thumb® Processor – DSP Instruction Extensions, Jazelle® Technology for Java® Acceleration – 16 Kbyte Data Cache, 16 Kbyte Instruction Cache, Write Buffer – 220 MIPS at 200 MHz – Memory Management Unit – EmbeddedICE™, Debug Communication Channel Support – Mid-level Implementation Embedded Trace Macrocell™ Bus Matrix – Nine 32-bit-layer Matrix, Allowing a Total of 28.8 Gbps of On-chip Bus Bandwidth – Boot Mode Select Option, Remap Command Embedded Memories – One 128 Kbyte Internal ROM, Single-cycle Access at Maximum Bus Matrix Speed – One 80 Kbyte Internal SRAM, Single-cycle Access at Maximum Processor or Bus Matrix Speed – One 16 Kbyte Internal SRAM, Single-cycle Access at Maximum Bus Matrix Speed Dual External Bus Interface (EBI0 and EBI1) – EBI0 Supports SDRAM, Static Memory, ECC-enabled NAND Flash and CompactFlash® – EBI1 Supports SDRAM, Static Memory and ECC-enabled NAND Flash DMA Controller (DMAC) – Acts as one Bus Matrix Master – Embeds...