Atmel PDC2
the PDC2 to control Bridge access. This avoids processor intervention and removes the processor interrupt handling overhead. This significantly reduces the number of clock cycles required for a data transfer and, as a result, improves the performance of the microcontroller and makes it more powerefficient.| Part No. | PDC2 |
|---|---|
| Datasheet | PDC2 Download |
| Manufacturer |  Atmel |
| Description | 32 bit Embedded ASIC Core Peripheral |
| Buy | Stock & Price |
FEATURES
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● Compatible with an Embedded ARM7TDMI™ Processor Generates Transfers to/from Serial Peripherals Such as UART, USART, SSC and SPI Supports Up to 12 Peripherals – Parameterizable on Request One ARM® Cycle Needed for a Transfer from Memory to Peripheral Two ARM Cycles Needed for a Transfer from Peripheral to Memory Fully Scan Testable up to 98% Fault Coverage Can be Directly Connected to the Atmel Implementation of the AMBA™ Bridge Not Fully Compatible with AMBA: Retract Response not Supported
DESCRIPTION
The Peripheral Data Controller 2 (PDC2) transfers data between on-chip peripherals such as the UART, USART, SSC and SPI and the on- and off-chip memories. This transfer is achieved via the AMBA Bridge using a simple arbitration mechanism between the AMBA System Bus (ASB) and the PDC2 to control Bridge access. The PDC2 channels are implemented in pairs, each pair being dedicated to a particular peripheral. One PDC2 channel in the pair is dedicated to the receiving channel and one to the transmitting channel of each UART, USART, SSC and SPI.
