AS4DDR264M72PBG - 64Mx72 DDR2 SDRAM iNTEGRATED Plastic Encapsulated Microcircuit

Description

On-Die-Termination: Registered High enables on data bus termination Differential input clocks, one set for each x16bits A7, A8, A9, A10, B7, Ax Input B8, B9, B10, C7, C8, C9, C10, D7 D8, D9, D10 DNU Future Input E8, E9m D9 BA0, BA1, BA2 Input A2, A3, A4, A13, A14, DQx Input/Output A15, B1, B2, B3,

Features

DDR2 Data rate = 667, 533, 400 Available in Industrial, Enhanced and Extended Temp Package:.
255 Plastic Ball Grid Array (PBGA), 25 x 32mm.
1.27mm pitch Differential data strobe (DQS, DQS#) per byte Internal, pipelined, double data rate architecture 4n-bit prefetch architecture DLL for alignment of DQ and DQS transitions with clock signal Eightinternal banks for concurrent operation (Per DDR2 SDRAM Die) Programmable Burst lengths: 4 or 8 Auto Refre.

Austin Semiconductor

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Datasheet Details

Part number	AS4DDR264M72PBG
Manufacturer	Austin Semiconductor
File Size	310.42 KB
Description	64Mx72 DDR2 SDRAM iNTEGRATED Plastic Encapsulated Microcircuit
Datasheet	AS4DDR264M72PBG Datasheet
Additional preview pages of the AS4DDR264M72PBG datasheet.

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Full PDF Text Transcription

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i PEM 4.8 G b SDRAM-DDR2 Gb Austin Semiconductor, Inc. AS4DDR264M72PBG 64Mx72 DDR2 SDRAM iNTEGRATED Plastic Encapsulated Microcircuit FEATURES DDR2 Data rate = 667, 533, 400 Available in Industrial, Enhanced and Extended Temp Package: • 255 Plastic Ball Grid Array (PBGA), 25 x 32mm • 1.27mm pitch Differential data strobe (DQS, DQS#) per byte Internal, pipelined, double data rate architecture 4n-bit prefetch architecture DLL for alignment of DQ and DQS transitions with clock signal Eightinternal banks for concurrent operation (Per DDR2 SDRAM Die) Programmable Burst lengths: 4 or 8 Auto Refresh and Self Refresh Modes (I/T Version) On Die Termination (ODT) Adjustable data – output drive strength 1.8V ±0.

Published: Sep 26, 2009 |