Austin Semiconductor AS5SS256K36A
The AS5SS256K36 employs high-speed, low-power CMOS designs that are fabricated using an advanced CMOS process. This 8Mb Synchronous Burst SRAM integrates a 256K x 36 SRAM core with advanced synchronous peripheral circuitry and a 2-bit burst counter. The synchronous inputs include all addresses, all data inputs, active LOW chip enable (CE\), two additional chip enables for easy depth expansion (CE2\, CE2), burst control inputs (ADSC\, ADSP\, ADV\), byte write enables (BWx\) and global write (GW\).| Part No. | AS5SS256K36A |
|---|---|
| Datasheet | AS5SS256K36A Download |
| Manufacturer |  Austin Semiconductor |
| Description | 256K x 36 SSRAM Flow-Through Synchronous Burst SRAM |
| Buy | Stock & Price |
FEATURES
! ! ! ! ! ! ! AS5SS256K36 & AS5SS256K36A PIN ASSIGNMENT (Top View) SSRAM ! ! ! ! ! ! Organized 256K x 36 Fast Clock and OE\ access times Single +3.3V +0.3V/-0.165V power supply (VDD) SNOOZE MODE for reduced-power standby Common data inputs and data outputs Individual BYTE WRITE control and GLOBAL WRITE Three chip enables for simple depth expansion and address pipelining Clock-controlled and registered addresses, data I/Os and control signals Internally self-timed WRITE cycle Burst control (interleaved or linear burst) Automatic power-down for portable applications 100-lead TQFP package for high density, high speed Low capacitive bus loading 100-pin TQFP (DQ) (2-chip enable version, “A” indicator) SA SA ADV\ ADSP\ ADSC\ OE\ BWE\ GW\ CLK Vss VDD SA BWa\ BWb\ BWc\ BWd\ CE2 CE\ SA SA 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 OPTIONS MARKING -8.5* -10 DQ No. 1001 A (PRELIMINARY) no indicator XT* IT Timing 8.5ns/10ns/100MHz 10ns/15ns/66MHz ! Packages 100-pin TQFP (2-chip enable) !
