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SRAM
Austin Semiconductor, Inc. 128K x 8 SRAM
WITH DUAL CHIP ENABLE ULTRA LOW POWER
AVAILABLE AS MILITARY SPECIFICATIONS
•MIL-STD-883, para. 1.2.2 compliant
MT5C1008(LL) Ultra Low Power
PIN ASSIGNMENT (Top View)
32-Pin DIP (C)
NC A16 A14 A12
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 26 27 25 24 23 22 21 20 19 18 17
VCC A15 CE2 WE A13 A8 A9 A11 OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3
FEATURES
• • • • • • • •
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A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND
High Speed: 30 ns Low active power: 715 mW worst case Low CMOS standby power: 3.3 mW worst case 2.0V data retention, Ultra Low 0.