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ADS5277 - 65MSPS Analog-to-Digital Converter

Download the ADS5277 datasheet PDF. This datasheet also covers the ADS5277_Burr variant, as both devices belong to the same 65msps analog-to-digital converter family and are provided as variant models within a single manufacturer datasheet.

General Description

The ADS5277 is a high-performance, CMOS, 65MSPS, 8-channel analog-to-digital converter (ADC).

Internal references are provided, simplifying system design requirements.

Low power consumption allows for the highest of system integration densities.

Key Features

  • Maximum Sample Rate: 65MSPS 10-Bit Resolution No Missing Codes Total Power Dissipation: Internal Reference: 911mW External Reference: 845mW CMOS Technology Simultaneous Sample-and-Hold 61.7dBFS SNR at 5MHz IF 3.3V Digital/Analog Supply Serialized LVDS Outputs Integrated Frame and Bit Patterns Option to Double LVDS Clock Output Currents Four Current Modes for LVDS Pin- and Format-Compatible Family TQFP-80 PowerPAD™ Package An integrated phase lock loop (PLL.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (ADS5277_Burr-BrownCorporation.pdf) that lists specifications for multiple related part numbers.

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
BurrĆBrown Products from Texas Instruments ADS5277 SBAS333C – FEBRUARY 2005 – REVISED SEPTEMBER 2005 8-Channel, 10-Bit, 65MSPS Analog-to-Digital Converter with Serial LVDS Interface FEATURES • • • • Maximum Sample Rate: 65MSPS 10-Bit Resolution No Missing Codes Total Power Dissipation: Internal Reference: 911mW External Reference: 845mW CMOS Technology Simultaneous Sample-and-Hold 61.7dBFS SNR at 5MHz IF 3.3V Digital/Analog Supply Serialized LVDS Outputs Integrated Frame and Bit Patterns Option to Double LVDS Clock Output Currents Four Current Modes for LVDS Pin- and Format-Compatible Family TQFP-80 PowerPAD™ Package An integrated phase lock loop (PLL) multiplies the incoming ADC sampling clock by a factor of 12.