CP5021 Datasheet | CHIP

Product Brief ETLINK Series CP5021_PB_Rev1.0, March,2005 Single E1 Transceiver .. OVERVIEW The CP5021 is a single E1 transceiver designed by Chiphomer Technology Limited. It integrates a short haul E1 line interface unit and an E1 framer into a single chip. Features CP5021 plete E1 transceiver Short haul line interface for clock/data recovery Programmable Waveform Shaper 32-bit or 64-bit crystal-less jitter attenuator Supports framed or unframed data receive and transmit LQFP64 Supports FAS, CAS, CCS and CRC4 formats -40 to 85 ℃ Dual 512-bit elastic buffers respectively for receive and transmit direction; controlled slip capability and slip indication Supports Sa and Si bits insertion and extraction Detects and generates Receive Carrier Loss (RCL), Synchronization Loss (RLOS), AIS, remote alarm, and remote multi-frame alarms CAS signaling insertion and extraction Integrated HDLC controller with two 64-byte buffers configurable for Sa bit and sub DS0 operation Provides three types of loopback for system testing purpose 8 bit parallel microprocessor interface supports either multiplexed or non-multiplexed bus with Intel or Motorola mode Statistic counters for Bipolar and code violations, CRC4 code word errors, FAS word errors, and E bits IEEE 1149.1 JTAG boundary scan 3.3 V CMOS technology with 5V tolerant I/O Power consumption less than 150m W MCLK2 RCL 8.192MHz Clock Synthesizer 8MCLK RCLK RLOS/LOTC HDLC controller Peak detection HDB3 Decoder RTIP RRING Rclk Rdata Receive Side Framer Data Clock Sync Data/Clock Recovery Receive Elastic Buffer RSER RSYSCLK RSYNC Equalizer Line Driver Jitter Attenuator Either Transmit or Receive Path Remote loopback Local loopback Framer loopback Receive Timing Generation HDB3 Encoder Wave Shaping LIU AIS Generation TTIP TRING Tclk Tdata Transmit Side...