CTS100ELT22DG Overview
The CTS100ELT22 is a dual CMOS/TTL to differential PECL translator. Because PECL (Positive ECL) levels are used, only VCC and ground are required. The small outline packaging and the low skew, dual gate design of the CTS100ELT22 makes it ideal for applications that require the translation of a clock and a data signal.
CTS100ELT22DG Key Features
- 0.5ns Typical Propogation Delay
- <100ps Typical Output to Output Skew
- Flow Through Pinouts
- Differential PECL Output
- RoHS pliant Pb Free Packages