CTS100ELT22TG Datasheet | CTS

FEATURES - 0.5ns Typical Propogation Delay - <100ps Typical Output to Output Skew - Flow Through Pinouts - Differential PECL Output - Ro HS pliant Pb Free Packages BLOCK DIAGRAM DESCRIPTION The CTS100ELT22 is a dual CMOS/TTL to differential PECL translator. Because PECL (Positive ECL) levels are used, only VCC and ground are required. The small outline packaging and the low skew, dual gate design of the CTS100ELT22 makes it ideal for applications that require the translation of a clock and a data signal. The CTS100ELT22 is a direct replacement for the ON Semi MC100ELT22, MC100LVELT22 and Micrel SY89322V. ENGINEERING NOTES When the D input is left floating, the Q output is forced HIGH, and the Q output is forced LOW. CTS100ELT22 Large Signal Bandwidth North Americas: +1-800-757-6686 - International: +1-508-435-6831 - Asia: +65-655-17551 - .ctscorp./semiconductors Specifications are subject to change without notice. 1 Rev B0215 CTS100ELT22 Dual CMOS/TTL to Differential PECL Translator MSOP8, SOIC8 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings are those values beyond which device life may be impaired. Symbol VCC VIN IOUT TA TSTG ESDHBM ESDMM ESDCDM Characteristic DC Power Supply Input Voltage Output Current Operating Temperature Range Storage Temperature Range Human Body Model Machine Model Charged Device Model Condition (VEE = 0V) (VEE = 0V) Continuous Surge Rating 0 to +8.0 0 to +6.0 50 100 -40 to +85 -65 to +150 2500 200 2500 Unit V V m A °C °C V V V Symbol IIH IIHH...