2305 Datasheet | CYT

DESCRIPTION The 2305 is the P-Channel logic enhancement mode power field effect transistor are produced using high cell density, DMOS trench technology. This high density process is especially tailored to minimize on-state resistance. These devices are particularly suited for low voltage application such as cellular phone and notebook puter power management and other batter powered circuits, and low in-line power loss are needed in a very small outine surface mount package. PIN CONFIGURATION SOT-23-3L 1.Gate 2.Source 3.Drain S05YA S: Subcontractor Y: Year Code A: Process Code SHENZHEN CYT OPTO-ELECTRONIC TECHNOLOGY CO.,LTD. Page 1 .szcyt. P Channel Enchancement Mode MOSFET -3.5A ABSOULTE MAXIMUM RATINGS (Ta = 25 Unless otherwise noted ) Parameter Drain-Source Voltage Gate-Source Voltage Continuous Drain Current (TJ=150 ) TA=25 TA=70 Pulsed Drain Current Continuous Source Current (Diode Conduction) Power Dissipation Operation Junction Temperature TA=25 TA=70 Storgae Temperature Range Thermal Resistance-Junction to Ambient Symbol VDSS VGSS ID IDM IS PD TJ TSTG R JA Typical -10 +/-12 -3.5 -2.8 -10 -1.6 1.25 0.8...