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2305 - 3.3V Zero-Delay Clock Buffer

General Description

The 2305 is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications.

The zero-delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10MHz to 133MHz.

Key Features

  • Phase-Lock Loop clock distribution.
  • 10MHz to 133MHz operating frequency.
  • Distributes one clock input to one bank of five outputs.
  • Zero input-output delay.
  • Output skew < 250ps.
  • Low jitter < 200ps cycle-to-cycle.
  • 2305-1 for Standard drive.
  • 2305-1H for High drive.
  • No external RC network required.
  • Operates at 3.3V VDD.
  • Power-down mode.
  • Available in SOIC/TSSOP packages.

📥 Download Datasheet

Datasheet Details

Part number 2305
Manufacturer Renesas
File Size 1.61 MB
Description 3.3V Zero-Delay Clock Buffer
Datasheet download datasheet 2305 Datasheet

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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2305 3.3V Zero-Delay Clock Buffer Datasheet Description The 2305 is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications. The zero-delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10MHz to 133MHz. The 2305 is an 8-pin version of the 2309. The 2305 accepts one reference input and drives out five low skew clocks. The -1H version of this device operates up to 133MHz frequency and has a higher drive than the -1 device. All parts have on-chip PLLs which lock to an input clock on the REF pin. The PLL feedback is on-chip and is obtained from the CLKOUT pad. In the absence of an input clock, the 2305 enters power down.