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2305 Datasheet 3.3v Zero-delay Clock Buffer

Manufacturer: Renesas

Overview: 2305 3.3V Zero-Delay Clock Buffer Datasheet.

Datasheet Details

Part number 2305
Manufacturer Renesas
File Size 1.61 MB
Description 3.3V Zero-Delay Clock Buffer
Datasheet 2305-Renesas.pdf

General Description

The 2305 is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications.

The zero-delay is achieved by aligning the phase between the ining clock and the output clock, operable within the range of 10MHz to 133MHz.

The 2305 is an 8-pin version of the 2309.

Key Features

  • Phase-Lock Loop clock distribution.
  • 10MHz to 133MHz operating frequency.
  • Distributes one clock input to one bank of five outputs.
  • Zero input-output delay.
  • Output skew < 250ps.
  • Low jitter < 200ps cycle-to-cycle.
  • 2305-1 for Standard drive.
  • 2305-1H for High drive.
  • No external RC network required.
  • Operates at 3.3V VDD.
  • Power-down mode.
  • Available in SOIC/TSSOP packages.

2305 Distributor