PACVGA105 Datasheet | California Micro Devices

PACVGA105 VGA Port panion Circuit Features - 7 channels of ESD protection designed to meet IEC-1000-4-2 Level-4 ESD requirements (8kV contact discharge) Very low loading capacitance from ESD protection diodes at less than 5pF typical TTL to CMOS level-translating buffers for the HSYNC and VSYNC lines Three independent supply pins (VCC, VRGB and VAUX) to facilitate operation with sub-micron Graphics Controller ICs High impedance pull-ups (50kΩ nominal to VAUX) for HSYNC and VSYNC inputs Pull-up resistors (1.8kΩ nominal to VCC) for DDC_CLK and DDC_DATA lines pact 16-pin QSOP package Lead-free version available Product Description The PACVGA105 incorporates 7 channels of ESD protection...