FEATURES
I Fast mode I2C bus compatible* I Max clock frequency: I 5 ms max write cycle time I Write protect feature - 400KHz for VCC=2.5V to 5.5V I Schmitt trigger filtered inputs for noise suppression I Low power CMOS technology I 64-byte page write buffer I Self-timed write cycle with auto-clear I Industrial and automotive temperature ranges – Bottom 1/4 array protected when WP at VIH (CAT24FC65) – Top 1/4 array protected when WP at VIH (CAT24FC66) I 1,000,000 program/erase cycles I 100 year data retention I 8-pin DIP, 8-pin SOIC (JEDEC), 8-pin SOIC (EIAJ), 8-pin TSSOP and TDFN packages DESCRIPTION
Catalyst’s advanced CMOS technology substantially reduces device power requirements. PIN CONFIGURATION DIP Package (P, L, GL) A0 A1 A2 VSS 1 2 3 4 8 7 6 5 VCC WP SCL SDA BLOCK DIAGRAM TDFN Package (RD2, ZD2) A0 1 A1 2 A2 3 VSS 4 8 VCC 7 WP 6 SCL 5 SDA EXTERNAL LOAD DOUT ACK VCC VSS WORD ADDRESS BUFFERS COLUMN DECODERS 512 SDA START/STOP LOGIC SENSE AMPS SHIFT REGISTERS SOIC Package (J, W,...
Catalyst Semiconductor
