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PROCESS
Small Signal Transistors
CP741V
PNP - Low VCE(SAT) Transistor Chip
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PROCESS DETAILS Process Die Size Die Thickness Base Bonding Pad Area Emitter Bonding Pad Area Top Side Metalization Back Side Metalization GEOMETRY GROSS DIE PER 5 INCH WAFER 54,330 PRINCIPAL DEVICE TYPES CMLT7410 CMPT7410 CMST7410 CMUT7410 EPITAXIAL PLANAR 17.7 x 17.7 MILS 7.1 MILS 3.8 x 3.8 MILS 3.8 x 3.8 MILS Al-Si - 30,000Å Au - 12,000Å
R2 (22-March 2010)
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PROCESS
CP741V
Typical Electrical Characteristics
R2 (22-March 2010)
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CP741V Datasheet
