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CEB6030LS2 - N-Channel Logic Level Enhancement Mode Field Effect Transistor

Download the CEB6030LS2 datasheet PDF. This datasheet also covers the CEB6030LS2_Chino variant, as both devices belong to the same n-channel logic level enhancement mode field effect transistor family and are provided as variant models within a single manufacturer datasheet.

Key Features

  • 30V , 52A , RDS(ON)=13.5m Ω @VGS=10V. RDS(ON)=20m Ω @VGS=4.5V. Super high dense cell design for extremely low RDS(ON). High power and current handling capability. TO-220 & TO-263 package. D G D GS CEB SERIES TO-263(DD-PAK) G D S CEP SERIES TO-220 S.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (CEB6030LS2_Chino-ExcelTechnology.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number CEB6030LS2
Manufacturer Chino-Excel Technology
File Size 51.48 KB
Description N-Channel Logic Level Enhancement Mode Field Effect Transistor
Datasheet download datasheet CEB6030LS2 Datasheet

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
CEP6030LS2/CEB6030LS2 PRELIMINARY N-Channel Logic Level Enhancement Mode Field Effect Transistor FEATURES 30V , 52A , RDS(ON)=13.5m Ω @VGS=10V. RDS(ON)=20m Ω @VGS=4.5V. Super high dense cell design for extremely low RDS(ON). High power and current handling capability. TO-220 & TO-263 package. D G D GS CEB SERIES TO-263(DD-PAK) G D S CEP SERIES TO-220 S ABSOLUTE MAXIMUM RATINGS (TC=25 C unless otherwise noted) Parameter Drain-Source Voltage Gate-Source Voltage Drain Current-Continuous -Pulsed Drain-Source Diode Forward Current Maximum Power Dissipation @Tc=25 C Derate above 25 C Operating and StorageTemperature Range Symbol VDS VGS ID IDM IS PD TJ, TSTG Limit 30 Ć20 52 156 52 50 0.