CRD5381 Datasheet | Cirrus Logic

Features Analog Performance  Advanced Multi-bit Delta-sigma Architecture  24-bit Conversion  120 d B Dynamic Range  -110 d B THD+N  Performance insensitivity to Input Clock Jitter     System Features  Output Sample Rate Determined by Input Digital Filter Characteristics  125 d B Stop-band Rejection  Phase-Matched Outputs  Word, Left/Right, or Fsync Clock No External Master Clock Required Easily Scalable for Additional Channels Sample Rates from 27 k Hz to 192 k Hz Four-Channel Time-Division Multiplexed Output Two Independent Stereo, Left-Justified Outputs LEFT RIGHT CS5381 A Quad Speed Slave Mode SDOUT SDIN CS8421 A Master Input Slave Ouput SDOUT TDM ENABLE Differential Analog Inputs 1-4 SDOUT A PCM Data Ouput/ Serial Clock Input Header, J4 LRCK INPUT SCLK INPUT TDM/SDOUT B 2 2 TDM IN LEFT RIGHT CS5381 B Quad Speed Slave Mode SDOUT SDIN CS8421 B Master Input Slave Output SDOUT http://.cirrus. Copyright © Cirrus Logic, Inc. 2005 (All Rights Reserved) MAY ‘05 DS563RD1 Description The bination of the CS5381 Analog-to-Digital Converter and CS8421 Asynchronous Sample Rate Converter creates an analog-to-digital conversion system with an asynchronous digital decimation filter that is virtually immune to interface or network jitter. In addition, the CS8421 adds a multi-channel Time Division Multiplexed (TDM) output format option. These unique features address many of the issues and design challenges associated with networked audio systems and other high-performance applications. In addition to the standard 24-bit audio data, the CS8421 adds the functionality to output properly dithered 32, 20, or 16-bit data. The CRD5381 was designed as a platform for easy evaluation of the jitter rejection, sample rate conversion, and time-division multiplexing capabilities of the CS8421 in the context of a A/D conversion system with an asynchronous decimation filter. The CRD5381 accepts four channels of balanced, analog audio input and...