CS2600 Datasheet | Cirrus Logic

Features - Clock frequency synthesizer incorporating delta-sigma fractional-N analog PLL - Generates low-jitter 6- 75 MHz clock (CLK_OUT) from 8- 75 MHz timing reference (REF_CLK_IN) - Fractional clock multiplier and jitter reduction using hybrid analog/digital PLL - Generates low-jitter 6- 75 MHz clock (CLK_OUT), synchronized to a 50 Hz- 30 MHz low-quality or intermittent frequency reference (CLK_IN) - Flexible timing reference source - External clock, external crystal, or built-in oscillator - High resolution PLL ratio (1 PPM) - Automatic rate control (ARC) for digital audio applications - Seamless transitions through changes in CLK_IN frequency reference - Customer-programmable startup configuration, using integrated one-time programmable (OTP) memory - Hardware and software control modes - I²C/SPI control port - Hardware control with no host processor required - Configurable auxiliary clock/status output - Minimal board space required - No external analog loop-filter ponents - Single-supply operation at 1.8 V or 3.3 V - 40 ps RMS period jitter (external timing reference), 35 ps RMS period jitter (oscillator reference) - Glitchless clock output generated from intermittent input - BCLK and FSYNC outputs (derived from CLK_OUT) for digital audio applications - Phase alignment with CLK_IN frequency reference Applications - Automotive audio systems - Digital audio systems - Network and USB audio interfaces - Io T sensor and transducer systems - Embedded systems XTAL_ IN /R EF_C LK_ IN XTAL_ OU T CLK_IN CONFIG1 I 2C _AD DR / SPI _C S/ CO NFI G2 I2C_SCL/S PI_SCK/CONFIG3 I2C_SDA/S PI_SDI/CONFIG4 SPI _SD O/ AU X2_ OU T/ C ON FI G5 VLDO_OTP/CONFIG 6 Divi der XTAL I nte rfac e Os cillat or Hardware/ Sof t wa re Mode Pin Mux Hybrid PLL Core Fractio nal-N Analog PLL Ratio...