DESCRIPTION
,J\ One full page (2~6 bytes) of RAM is I~cated .(on chip) ~~ncurrently at Page a and ~a~ 1, allowing Zero Page Addressing and stack operations With no additional RAM. """,,,., """",.j \ An 8-bit Bi-Directional 1/0 Port is located on-chip with the Output Register at .,. ti~re&&:Q, a'o.~ and the Data-Direction Register at Address 0 a a a. The 110 Port is bit-by-bit prog~~ ~I~,. ,"""''''' I) The Three-State sixteen-bit Address Bus allows Direct Memory A{c\,.~ .\lfo'Mf.) and multi- processor systems sharing a common memory. ''\",\,\\,i,/l''''''''''''',\,,,,,,~:'7 The internal processor architecture is identical to the MOS TeG~●n"e:l'tGg~. provide software compatibility. '\ . F
