DESCRIPTION
Reference input frequencies are automatically detected, and inputs are individually monitored for quality. Active reference selection may be manual or automatic. All reference switches are hitless. Synchronized outputs may be programmed for a wide variety of SONET and SDH frequencies. Two independent clock generators provide the standardized T0 and T4 functions. Each clock generator includes a DPLL (Digital Phase-Locked Loop), which may operate in the Freerun, Synchronized, and Holdover modes. Both clock generators support master/ slave operation for redundant applications. ConnorWinfield’s proprietary SyncLinkTM Cross-couple data link provides master/slave phase information and state data to ensure seamless side switches. A standard SPI serial bus interface or parallel bus provide access to the STC4130’s comprehensive, yet simple to use internal control and status registers. The device operates with an external OCXO or TCXO as its MCLK at either 10 or 20 MHz. STC4130 Featu...
Connor-Winfield
