DESCRIPTION
Reference input frequencies are automatically detected, and inputs are individually monitored for quality. Active reference selection may be manual or automatic. All reference switches are hitless. Synchronized outputs may be programmed for a wide variety of SONET and SDH as well as Synchronous Ethernet frequencies. Two independent timing generators, T0 and T4, provide the essential functions for Synchronous Equipment Timing Source (SETS). Each timing generator includes a DPLL (Digital Phase-Locked Loop), which may operate in the Freerun, Synchronized, and Holdover modes. Both timing generators support master/slave operation for redundant applications. The proprietary SyncLinkTM cross-couple data link provides master/slave phase information and state data to ensure seamless side switches. A standard SPI serial bus interface provide access to the STC5230’s comprehensive, yet simple to use internal control and status registers. The device operates with an external OCXO or TCXO as its MCLK at 20 MHz.
Connor-Winfield
