CY24271 Description
For a plete list of related documentation, click here. F San Jose, CA 95134-1709 408-943-2600 Revised May 20, 2016 CY24271 Contents Pinouts ..............................................
CY24271 Key Features
- Meets Rambus Extended Data Rate (XDR™) clocking requirements
- 25 ps typical cycle-to-cycle jitter
- 135 dBc/Hz typical phase noise at 20 MHz offset
- 100 or 133 MHz differential clock input
- 300-800 MHz high speed clock support
- Quad (open drain) differential output drivers
- Spread Aware™
- 2.5 V operation
- 28-pin TSSOP package
- 198 Champion Court Document Number: 001-00411 Rev. -F