Description
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198 Champion Court Document N
Features
- Meets Rambus Extended Data Rate (XDR™) clocking requirements.
- 25 ps typical cycle-to-cycle jitter.
- 135 dBc/Hz typical phase noise at 20 MHz offset.
- 100 or 133 MHz differential clock input.
- 300.
- 800 MHz high speed clock support.
- Quad (open drain) differential output drivers.
- Supports frequency multipliers: 3, 4, 5, 6, 8, 9/2, 15/2, and 15/4.
- Spread Aware™.
- 2.5 V operation.
- 28-pin TSSOP package
Functional.
CY24271 Datasheet
