CY28400 Datasheet | Cypress

100-MHz Differential Buffer for PCI Express and SATA Features - CK409 or CK410 panion buffer - Four differential 0.7v clock pairs - Individual OE controls - Low CTC jitter (< 50 ps) - Programmable bandwidth - SRC_STOP# power management control - SMBus Block/Byte/Word Read and Write support - 3.3V operation - PLL Bypass-configurable - Divide by 2 programmable outputs - 28-pin SSOP package Functional Description The CY28400 is a differential buffer and serves as a panion device to the CK409 or CK410 clock generator. The device is capable of distributing the Serial Reference Clock (SRC) in PCI Express and SATA implementations. Block Diagram Pin Configuration DIFT1 OE_(1,6) SRC_STOP# PWRDWN# Output Control DIFC1 DIFT2 SCLK SDATA SMBus Controller Output Buffer DIFC2 PLL/BYPASS# SRCT_IN SRCC_IN DIFT5 DIFC5 VDD SRCT_IN SRCC_IN VSS VDD DIFT1 DIFC1 OE_1 DIFT2 DIFC2 VDD PLL/BYPASS# SCLK SDATA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 25 24 23 22 21 20 19 18 17 16 15 VDD_A VSS_A IREF VSS VDD DIFT6 DIFC6 0E_6 DIFT5 DIFC5 VDD HIGH_BW# SRC_STOP#...