CY29350 Datasheet | Cypress

2.5V or 3.3V, 200-MHz, 9-Output Clock Driver Features - Output frequency range: 25 MHz to 200 MHz - Input frequency range: 6.25 MHz to 31.25 MHz - 2.5V or 3.3V operation - Split 2.5V/3.3V outputs - ±2.5% max Output duty cycle variation - Nine Clock outputs: Drive up to 18 clock lines .. - Two reference clock inputs: Xtal or LVCMOS - 150-ps max output-output skew - Phase-locked loop (PLL) bypass mode - Spread Aware™ - Output enable/disable - Pin-patible with MPC9350 - Industrial temperature range: - 40°C to +85°C - 32-pin 1.0mm TQFP package Functional Description The CY29350 is a low-voltage high-performance 200-MHz PLL-based clock driver designed for high speed clock distribution applications. The CY29350 Features Xtal and LVCMOS reference clock inputs and provides nine outputs partitioned in four banks of 1, 1, 2, and 5 outputs. Bank A divides the VCO output by 2 or 4 while the other banks divide by 4 or 8 per SEL(A:D) settings, see . These dividers allow output to input ratios of 16:1, 8:1, 4:1, and 2:1. Each LVCMOS patible output can drive 50Ω series or parallel terminated transmission lines. For series terminated transmission lines, each output can drive one or two traces giving the device an effective fanout of 1:18. The PLL is ensured stable given that the VCO is configured to run between 200 MHz to 500 MHz. This allows a wide range of output frequencies from 25 MHz to 200 MHz. The internal VCO is running at multiples of the input reference clock set by the feedback divider, see Table 1. When PLL_EN is LOW, PLL is bypassed and the reference clock directly feeds the output dividers. This mode is fully static and the minimum input clock frequency specification does not apply. Block Diagram Pin Configuration SELA PLL_EN REF_SEL PLL_EN TCLK XIN XOUT Phase Detector VCO 200 500MHz ÷2 /...