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CY2XP304 - High-Frequency Programmable PECL Clock Generation Module

Description

SER_CLK Serial Interface Clock SER_DATA Serial Interface Data PLL_MULT PLL Multiplier Select Input, Internal pull-up resistor, see Frequency Table CLK_SEL INA,INAB NC Clock Select Input, Internal Pull down.

HIGH select INA/INAB, Internal PLL is bypassed.

Features

  • Period jitter peak-peak 125MHz(max. ) = 55 ps.
  • Four low-skew LVPECL outputs.
  • Phase-locked loop (PLL) multiplier select.
  • Serially-configurable multiply ratios.
  • Eight-bit feedback counter and six-bit reference counter for high accuracy.
  • HSTL inputs.
  • HSTL-to-LVPECL level translation.
  • 125- to 500-MHz output range for high-speed.

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Full PDF Text Transcription

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CY2XP304 High-Frequency Programmable PECL Clock Generation Module Features • Period jitter peak-peak 125MHz(max.) = 55 ps • Four low-skew LVPECL outputs • Phase-locked loop (PLL) multiplier select • Serially-configurable multiply ratios • Eight-bit feedback counter and six-bit reference counter for high accuracy • HSTL inputs—HSTL-to-LVPECL level translation • 125- to 500-MHz output range for high-speed applications • High-speed PLL bypass mode to 1.5 GHz • 36-VFBGA, 6 × 8 × 1 mm • 3.
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