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CY2XP306 - High-frequency Programmable PECL Clock Generation Module

Description

CY2XP306 PLL_MULT PLL Multiplier Select Input, Internal pull-up resistor, see Frequency Table LVPECL Output Divider Select; Internal Pull-Down, see Output Frequency Table LVPECL Output Divider Select; Internal Pull-Down, see Output Frequency Table No Connect SER_DATA Serial Interface Data SER_CLK

Features

  • 60 ps typical Cycle-to-Cycle Jitter.
  • 30 ps typical Output-Output Skew.
  • Phase-locked loop (PLL) multiplier select.
  • LVTTL or XO Input; Six LVPECL Outputs.
  • Selectable Output Divider (/2).
  • 1.
  • 133 MHz Input Frequency Range.
  • 62.5.
  • 500 MHz Output Frequency Range.
  • 36-pin VFBGA, 6 × 8 × 1 mm.
  • 3.3V operation.
  • Serially Configurable Multiply Ratios Block Diagram QA1 FSELA QA1# PLL_MULT 0 1 QA2 QA2# Q.

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Full PDF Text Transcription

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PRELIMINARY CY2XP306 High-frequency Programmable PECL Clock Generation Module Features • 60 ps typical Cycle-to-Cycle Jitter • 30 ps typical Output-Output Skew • Phase-locked loop (PLL) multiplier select • LVTTL or XO Input; Six LVPECL Outputs • Selectable Output Divider (/2) • 1–133 MHz Input Frequency Range • 62.5–500 MHz Output Frequency Range • 36-pin VFBGA, 6 × 8 × 1 mm • 3.
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