CY2XP306 Description
CY2XP306 PLL_MULT PLL Multiplier Select Input, Internal pull-up resistor, see Frequency Table LVPECL Output Divider Select; Internal Pull-Down, see Output Frequency Table LVPECL Output Divider Select; Internal Pull-Down, see Output Frequency Table No Connect SER_DATA Serial Interface Data SER_CLK Serial Interface Clock Example PLL Output Frequency 311.04 MHz 312.5 MHz 155.52 MHz 156.25 MHz 311.04 MHz Table.
CY2XP306 Key Features
- 60 ps typical Cycle-to-Cycle Jitter
- 30 ps typical Output-Output Skew
- Phase-locked loop (PLL) multiplier select
- LVTTL or XO Input; Six LVPECL Outputs
- Selectable Output Divider (/2)
- 1-133 MHz Input Frequency Range
- 62.5-500 MHz Output Frequency Range
- 36-pin VFBGA, 6 × 8 × 1 mm
- 3.3V operation
- Serially Configurable Multiply Ratios