Datasheet Details
| Part number | CY3120 |
|---|---|
| Manufacturer | Cypress (now Infineon) |
| File Size | 112.69 KB |
| Description | CPLD Development Software for PC |
| Datasheet |
 CY3120 Datasheet
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General Description
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Behavioral VHDL and Verilog (IFTHENELSE; CASE)
Boolean
Aldec Active-HDL™ FSM graphical Finite State Machine editor
Structural Verilog and VHDL
Designs can include multiple entry methods (but only one HDL language) in a single design.
UltKey Features
- VHDL (IEEE 1076 and 1164) and Verilog (IEEE 1364) high-level language compilers with the following features:.
- Designs are portable across multiple devices and/or EDA environments w w.
- Facilitates the use of industry-standard simulation and synthesis tools for board and system-level design w . D a S a t e e h U 4 t . m o c CY3120 Warp® CPLD Development Software for PC.
- User selectable speed and/or area optimization on a block-by-block basis.