Description
:
Behavioral VHDL and Verilog (IFTHENELSE; CASE)
Boolean
Aldec Active-HDL™ FSM graphical Finite State Machine editor
Structural Verilog and VHDL
Designs can include multiple entry methods (but only one HDL language) in a single design.
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Features
- VHDL (IEEE 1076 and 1164) and Verilog (IEEE 1364) high-level language compilers with the following features:.
- Designs are portable across multiple devices and/or EDA environments
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- Facilitates the use of industry-standard simulation and synthesis tools for board and system-level design
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CY3120
Warp® CPLD Development Software for PC.
- User selectable speed and/or area optimization on a block-by-block basis.
CY3120 Datasheet
