Description
:
Graphical HDL Block Diagram editor and a library of blocks from Aldec
Aldec Active-HDL™ FSM graphical Finite State Machine editor
Behavioral VHDL and Verilog (IFTHENELSE; CASE)
Boolean
Structural Verilog and VHDL
Designs can include multi
Features
- h S a at . D w w w
CY3128
Warp Professional™ CPLD Software.
- Support for all Cypress Programmable Logic Devices.
- PSI™ (Programmable Serial Interface™).
- Delta39K™ CPLDs.
- Quantum38K™ CPLDs.
- Ultra37000™ CPLDs.
- FLASH370i™ CPLDs.
- MAX340™ CPLDs.
- Industry standard PLDs (16V8, 20V8, 22V10).
- VHDL and Verilog timing model output for use with third-party simulators.
- Active-HDL™ Sim Release 4.1 timing simulation from A.
CY3128 Datasheet
