CY7C037 Datasheet | Cypress

25/0251 CY7C027/028 CY7C037/038 32K/64K x 16/18 Dual-Port Static RAM Features - True Dual-Ported memory cells which allow simultaneous access of the same memory location - 32K x 16 organization (CY7C027) - 64K x 16 organization (CY7C028) - 32K x 18 organization (CY7C037) - 64K x 18 organization (CY7C038) - 0.35-micron CMOS for optimum speed/power - High-speed access: 12[1]/15/20 ns - Low operating power - Active: ICC = 180 m A (typical) - Standby: ISB3 = 0.05 m A (typical) - Fully asynchronous operation - Automatic power-down - Expandable data bus to 32/36 bits or more using Master/Slave chip select when using more than one device - On-chip arbitration logic - Semaphores included to permit software handshaking between ports - INT flags for port-to-port munication - Separate upper-byte and lower-byte control - Dual Chip Enables - Pin select for Master or Slave - mercial and industrial temperature ranges - Available in 100-pin TQFP - Pin-patible and functionally equivalent to IDT7027 Logic Block Diagram R/WL UBL R/WR UBR CE0L CE1L LBL OEL CE0R CE1R LBR...