CY7C037 Overview
Various arbitration schemes are included on the devices to handle situations when multiple processors access the same piece of data. Two ports are provided, permitting independent, asynchronous access for reads and writes to any location in memory. The devices can be utilized as standalone 16/18-bit dual-port static RAMs or multiple devices can be bined in order to function as a 32/36-bit or wider master/slave...
CY7C037 Key Features
- True Dual-Ported memory cells which allow simultaneous access of the same memory location
- 32K x 16 organization (CY7C027)
- 64K x 16 organization (CY7C028)
- 32K x 18 organization (CY7C037)
- 64K x 18 organization (CY7C038)
- 0.35-micron CMOS for optimum speed/power
- High-speed access: 12[1]/15/20 ns
- Low operating power
- Active: ICC = 180 mA (typical)
- Standby: ISB3 = 0.05 mA (typical)