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CY7C09169 - 8K/16K x 9 Synchronous Dual-Port Static RAM

This page provides the datasheet information for the CY7C09169, a member of the CY7C09159 8K/16K x 9 Synchronous Dual-Port Static RAM family.

Description

The CY7C09159 and CY7C09169 are high speed synchronous CMOS 8K and 16K x 9 dual-port static RAMs.

Two ports are provided, permitting independent, simultaneous access for reads and writes to any location in memory.

Features

  • True Dual-Ported memory cells which allow simultaneous access of the same memory location.
  • 2 Flow-Through/Pipelined devices.
  • 8K x 9 organization (CY7C09159).
  • 16K x 9 organization (CY7C09169).
  • 3 Modes.
  • Flow-Through.
  • Pipelined.
  • Burst.
  • Pipelined output mode on both ports allows fast 100-MHz cycle time.
  • 0.35-micron CMOS for optimum speed/power v.
  • High-speed clock to data access 6.5/7.5/12 ns (max. ).

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Datasheet preview – CY7C09169

Datasheet Details

Part number CY7C09169
Manufacturer Cypress Semiconductor
File Size 452.60 KB
Description 8K/16K x 9 Synchronous Dual-Port Static RAM
Datasheet download datasheet CY7C09169 Datasheet
Additional preview pages of the CY7C09169 datasheet.

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Other Datasheets by Cypress Semiconductor
  • CY7C09159 - 8K/16K x 9 Synchronous Dual-Port Static RAM
  • CY7C09159AV - 3.3-V 8 K x 9 Synchronous Dual Port Static RAM
  • CY7C09179V - (CY7C09xx9V) 3.3V 32K/64K/128K x 8/9 Synchronous Dual-Port Static RAM
  • CY7C09189 - (CY7C09xx9) 64K/128K x 8/9 Synchronous Dual-Port Static RAM
  • CY7C09189V - (CY7C09xx9V) 3.3V 32K/64K/128K x 8/9 Synchronous Dual-Port Static RAM
  • CY7C09199 - (CY7C09xx9) 64K/128K x 8/9 Synchronous Dual-Port Static RAM
  • CY7C09199V - (CY7C09xx9V) 3.3V 32K/64K/128K x 8/9 Synchronous Dual-Port Static RAM
  • CY7C09079V - (CY7C09xx9V) 3.3V 32K/64K/128K x 8/9 Synchronous Dual-Port Static RAM

Full PDF Text Transcription

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51 fax id: 5218 PRELIMINARY CY7C09159 CY7C09169 8K/16K x 9 Synchronous Dual-Port Static RAM Features • True Dual-Ported memory cells which allow simultaneous access of the same memory location • 2 Flow-Through/Pipelined devices — 8K x 9 organization (CY7C09159) — 16K x 9 organization (CY7C09169) • 3 Modes — Flow-Through — Pipelined — Burst • Pipelined output mode on both ports allows fast 100-MHz cycle time • 0.35-micron CMOS for optimum speed/power v • High-speed clock to data access 6.5/7.5/12 ns (max.) • Low operating power — Active= 200 mA (typical) — Standby= 0.
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