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CY7C09289V - 3.3 V 16K / 32K / 64K x 16 / 18 Synchronous Dual-Port Static RAM

Download the CY7C09289V datasheet PDF. This datasheet also covers the CY7C09269V variant, as both devices belong to the same 3.3 v 16k / 32k / 64k x 16 / 18 synchronous dual-port static ram family and are provided as variant models within a single manufacturer datasheet.

Features

  • True dual-ported memory cells that allow simultaneous access of the same memory location.
  • Six flow through/pipelined devices:.
  • 16K × 16 / 18 organization (CY7C09269V/369V).
  • 32K × 16 organization (CY7C09279V).
  • 64K × 16 / 18 organization (CY7C09289V/389V).
  • Three modes:.
  • Flow through.
  • Pipelined.
  • Burst.
  • Pipelined output mode on both ports allows fast 100 MHz operation.
  • 0.35 micron CMOS for optimum speed and power.
  • High speed clock to data.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (CY7C09269V-CypressSemiconductor.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

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Other Datasheets by Cypress (Infineon)

Part Number Description
CY7C09289 32K/64K X 16/18 Synchronous Dual Port Static RAM
CY7C09269V 3.3 V 16K / 32K / 64K x 16 / 18 Synchronous Dual-Port Static RAM
CY7C09279 32K/64K X 16/18 Synchronous Dual Port Static RAM
CY7C09279V 3.3 V 16K / 32K / 64K x 16 / 18 Synchronous Dual-Port Static RAM
CY7C09079V (CY7C09xx9V) 3.3V 32K/64K/128K x 8/9 Synchronous Dual-Port Static RAM

Full PDF Text Transcription

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CY7C09269V/79V/89V CY7C09369V/89V 3.3 V 16K / 32K / 64K × 16 / 18 Synchronous Dual-Port Static RAM 3.3 V 16K / 32K / 64K × 16 / 18 Synchronous Dual-Port Static RAM Features ■ True dual-ported memory cells that allow simultaneous access of the same memory location ■ Six flow through/pipelined devices: ❐ 16K × 16 / 18 organization (CY7C09269V/369V) ❐ 32K × 16 organization (CY7C09279V) ❐ 64K × 16 / 18 organization (CY7C09289V/389V) ■ Three modes: ❐ Flow through ❐ Pipelined ❐ Burst ■ Pipelined output mode on both ports allows fast 100 MHz operation ■ 0.35 micron CMOS for optimum speed and power ■ High speed clock to data access: 7.5[1], 9, 12 ns (max) ■ 3.
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