CY7C1020D
Overview
- Pin- and function-compatible with CY7C1020B
- High speed ❐ tAA = 10 ns
- Low active power ❐ ICC = 80 mA @ 10 ns
- Low complementary metal oxide semiconductor (CMOS) standby power ❐ ISB2 = 3 mA
- 2.0 V data retention
- Automatic power-down when deselected
- CMOS for optimum speed/power
- Independent control of upper and lower bits
- Available in Pb-free 44-pin 400-Mil wide Molded SOJ and 44-pin thin small outline package (TSOP) II packages Functional Description The CY7C1020D [1] is a high-performance CMOS static RAM organized as 32,768 words by 16 bits. This device has an automatic power-down feature that significantly reduces power consumption when input and output pins (IO0 through IO15) are placed in a high-impedance state when: Logic Block Diagram
