CY7C106B Datasheet | Cypress

1CY7C1006B CY7C106B CY7C1006B 256K x 4 Static RAM Features - High speed - t AA = 12 ns - CMOS for optimum speed/power - Low active power - 495 m W - Low standby power - 275 m W - 2.0V data retention (optional) - 100 µW - Automatic power-down when deselected - TTL-patible inputs and outputs Enable (CE), an active LOW Output Enable (OE), and three-state drivers. These devices have an automatic power-down feature that reduces power consumption by more than 65% when the devices are deselected. Writing to the devices is acplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the four I/O pins (I/O0 through I/O3) is then written into the location specified on the address pins (A0 through A17). Reading from the devices is acplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the four I/O pins. The four input/output pins (I/O0 through I/O3) are placed in a high-impedance state when the devices are deselected (CE HIGH), the outputs are disabled (OE HIGH), or during a write operation (CE and WE LOW). The CY7C106B is available in a standard 400-mil-wide SOJ; the CY7C1006B is available in a standard 300-mil-wide SOJ. Functional Description The CY7C106B and CY7C1006B are high-performance CMOS static RAMs organized as 262,144 words by 4 bits. Easy memory expansion is provided by an active LOW Chip Logic Block Diagram Pin Configuration SOJ Top View A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 CE OE GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 INPUT BUFFER A1 A2 A3 A4 A5 A6 A7 A8 A9 ROW DECODER SENSE AMPS I/O3 I/O2 I/O1 I/O0 VCC A17 A16 A15 A14 A13 A12 A11 NC I/O3 I/O2 I/O1 I/O0 WE C106B- 2 512 x 512 x 4 ARRAY COLUMN...