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CY7C1145KV18 - 18-Mbit QDR II+ SRAM Four-Word Burst Architecture

Download the CY7C1145KV18 datasheet PDF. This datasheet also covers the CY7C1143KV18 variant, as both devices belong to the same 18-mbit qdr ii+ sram four-word burst architecture family and are provided as variant models within a single manufacturer datasheet.

Key Features

  • Separate independent read and write data ports.
  • Supports concurrent transactions.
  • 450-MHz clock for high bandwidth.
  • Four-word burst for reducing address bus frequency.
  • Double data rate (DDR) Interfaces on both read and write ports (data transferred at 900 MHz) at 450 MHz.
  • Available in 2.0 clock cycle latency.
  • Two input clocks (K and K) for precise DDR timing.
  • SRAM uses rising edges only.
  • Echo clocks (CQ and CQ) simplify data capture in high-speed sys.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (CY7C1143KV18-CypressSemiconductor.pdf) that lists specifications for multiple related part numbers.

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
 CY7C1143KV18/CY7C1145KV18 18-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.0 Cycle Read Latency) 18-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.0 Cycle Read Latency) Features ■ Separate independent read and write data ports ❐ Supports concurrent transactions ■ 450-MHz clock for high bandwidth ■ Four-word burst for reducing address bus frequency ■ Double data rate (DDR) Interfaces on both read and write ports (data transferred at 900 MHz) at 450 MHz ■ Available in 2.