Datasheet Summary
CY7C1141V18 CY7C1156V18 CY7C1143V18 CY7C1145V18
18-Mbit QDR™-II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency)
Features
Separate Independent read and write data ports
- Supports concurrent transactions
- 300 MHz to 375 MHz clock for high bandwidth
- 4-Word Burst for reducing address bus frequency
- Double Data Rate (DDR) interfaces on both read and write ports (data transferred at 750 MHz) at 375 MHz
- Read latency of 2.0 clock cycles
- Two input clocks (K and K) for precise DDR timing
- SRAM uses rising edges only
- Echo clocks (CQ and CQ) simplify data capture in high speed systems
- Single multiplexed address input bus latches address inputs for both read and write ports
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