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CY7C1156V18 Datasheet (cy7c11xxv18) Sram 4-word Burst Architecture

Manufacturer: Cypress (now Infineon)

Overview: CY7C1141V18 CY7C1156V18 CY7C1143V18 CY7C1145V18 18-Mbit QDR™-II+ SRAM 4-Word Burst Architecture (2.

This datasheet includes multiple variants, all published together in a single manufacturer document.

General Description

The CY7C1141V18, CY7C1156V18, CY7C1143V18, and CY7C1145V18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II+ architecture.

QDR-II+ architecture consists of two separate ports to access the memory array.

The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations.

Key Features

  • Separate Independent read and write data ports.
  • Supports concurrent transactions.
  • 300 MHz to 375 MHz clock for high bandwidth.
  • 4-Word Burst for reducing address bus frequency.
  • Double Data Rate (DDR) interfaces on both read and write ports (data transferred at 750 MHz) at 375 MHz.
  • Read latency of 2.0 clock cycles.
  • Two input clocks (K and K) for precise DDR timing.
  • SRAM uses rising edges only.
  • Echo clocks (CQ and CQ) simplify data capture in high speed syste.

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More Datasheets from Cypress (now Infineon)

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CY7C1150KV18 18-Mbit DDR II+ SRAM Two-Word Burst Architecture
CY7C1150V18 (CY7C11xxV18) 18-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1157V18 (CY7C11xxV18) 18-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1141V18 (CY7C11xxV18) SRAM 4-Word Burst Architecture
CY7C1143KV18 18-Mbit QDR II+ SRAM Four-Word Burst Architecture
CY7C1143V18 (CY7C11xxV18) SRAM 4-Word Burst Architecture
CY7C1145KV18 18-Mbit QDR II+ SRAM Four-Word Burst Architecture
CY7C1145V18 (CY7C11xxV18) SRAM 4-Word Burst Architecture
CY7C1146V18 (CY7C11xxV18) 18-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1148KV18 18-Mbit DDR II+ SRAM Two-Word Burst Architecture