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CY7C1241V18 - 36-Mbit QDR-II SRAM 4-Word Burst Architecture

General Description

The CY7C1241V18, CY7C1256V18, CY7C1243V18, and CY7C1245V18 are 1.8V Synchronous Pipelined SRAMs, equipped with Quad Data Rate-II+ (QDR-II+) architecture.

QDR-II+ architecture consists of two separate ports to access the memory array.

Key Features

  • Separate independent read and write data ports.
  • Supports concurrent transactions.
  • 300 MHz to 375 MHz clock for high bandwidth.
  • 4-Word Burst for reducing address bus frequency.
  • Double Data Rate (DDR) interfaces on both read and write ports (data transferred at 750 MHz) at 375 MHz.
  • Read latency of 2.0 clock cycles.
  • Two input clocks (K and K) for precise DDR timing.
  • SRAM uses rising edges only.
  • Echo clocks (CQ and CQ).

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Other Datasheets by Cypress (now Infineon)

Part Number Description
CY7C12411KV18 36-Mbit QDR II SRAM 4-Word Burst Architecture
CY7C1241KV18 36-Mbit QDR II SRAM 4-Word Burst Architecture
CY7C12431KV18 36-Mbit QDR II SRAM 4-Word Burst Architecture
CY7C1243KV18 36-Mbit QDR II SRAM 4-Word Burst Architecture
CY7C1243V18 36-Mbit QDR-II SRAM 4-Word Burst Architecture

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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CY7C1241V18 CY7C1256V18 CY7C1243V18 CY7C1245V18 36-Mbit QDR™-II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) Features • Separate independent read and write data ports — Supports concurrent transactions • 300 MHz to 375 MHz clock for high bandwidth • 4-Word Burst for reducing address bus frequency • Double Data Rate (DDR) interfaces on both read and write ports (data transferred at 750 MHz) at 375 MHz • Read latency of 2.