CY7C1243KV18 Datasheet | Cypress

36-Mbit QDR II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) 36-Mbit QDR® II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) CY7C1241KV18, CY7C1256KV18 CY7C1243KV18, CY7C1245KV18 ® Features - Configurations With Read Cycle Latency of 2.0 cycles: CY7C1241KV18 - 4 M × 8 CY7C1256KV18 - 4 M × 9 CY7C1243KV18 - 2 M × 18 CY7C1245KV18 - 1 M × 36 Separate independent read and write data ports - Supports concurrent transactions 450 MHz clock for high bandwidth 4-word burst for reducing address bus frequency Double data rate (DDR) interfaces on both read and write ports (data transferred at 900 MHz) at 450 MHz Available in 2.0 clock cycle latency Two input clocks (K and K) for precise DDR timing - SRAM uses rising edges only Echo clocks (CQ and CQ) simplify data capture in high speed systems Data valid pin (QVLD) to indicate valid data on the output Single multiplexed address input bus latches address inputs for read and write ports Separate port selects for depth expansion Synchronous internally self-timed writes QDR® II+ operates with 2.0 cycle read latency when DOFF is asserted HIGH Operates similar to QDR I device with 1 cycle read latency when DOFF is asserted LOW Available in × 8, × 9, × 18, and × 36 configurations Full data coherency, providing most current data Core VDD = 1.8 V ± 0.1 V; I/O VDDQ = 1.4 V to VDD[1] - Supports both 1.5 V and 1.8 V I/O supply HSTL inputs and variable drive HSTL output buffers Available in 165-ball FBGA package (13 × 15 × 1.4 mm) Offered in both Pb-free and non Pb-free packages JTAG 1149.1 patible test access port Phase-locked loop (PLL) for accurate data placement Description - - - - - Functional Description The CY7C1241KV18, CY7C1256KV18, CY7C1243KV18, and CY7C1245KV18 are 1.8 V synchronous pipelined SRAMs, equipped with QDR II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has...