CY7C1243KV18 Overview
Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations.
CY7C1243KV18 Key Features
- 4 M × 8 CY7C1256KV18
- 4 M × 9 CY7C1243KV18
- 2 M × 18 CY7C1245KV18
- 1 M × 36
- Supports concurrent transactions 450 MHz clock for high bandwidth 4-word burst for reducing address bus frequency Double
- Supports both 1.5 V and 1.8 V I/O supply HSTL inputs and variable drive HSTL output buffers Available in 165-ball FBGA p
- Functional Description