CY7C25422KV18 - 72-Mbit QDR II+ SRAM Two-Word Burst Architecture

Datasheet Summary

Features

Separate independent read and write data ports.
Supports concurrent transactions.
333 MHz clock for high bandwidth.
Two-word burst for reducing address bus frequency.
Double Data Rate (DDR) interfaces on both read and write ports (data transferred at 666 MHz) at 333 MHz.
Available in 2.0 clock cycle latency.
Two input clocks (K and K) for precise DDR timing.
SRAM uses rising edges only.
Echo clocks (CQ and CQ) simplify data capture in high speed syst.

Cypress Semiconductor

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Datasheet Details

Part number	CY7C25422KV18
Manufacturer	Cypress Semiconductor
File Size	557.73 KB
Description	72-Mbit QDR II+ SRAM Two-Word Burst Architecture
Datasheet	CY7C25422KV18 Datasheet
Additional preview pages of the CY7C25422KV18 datasheet.

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Full PDF Text Transcription

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CY7C25422KV18 72-Mbit QDR® II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) with ODT 72-Mbit QDR® II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) with ODT Features ■ Separate independent read and write data ports ❐ Supports concurrent transactions ■ 333 MHz clock for high bandwidth ■ Two-word burst for reducing address bus frequency ■ Double Data Rate (DDR) interfaces on both read and write ports (data transferred at 666 MHz) at 333 MHz ■ Available in 2.

Published: Mar 14, 2017 |