CY7C1302CV25 Datasheet 9-mbit Burst Of Two Pipelined Srams

Manufacturer: Cypress (now Infineon)

Overview: www.DataSheet4U.com PREMILINARY CY7C1302CV25 9-Mbit Burst of Two Pipelined SRAMs with QDR™.

Datasheet Details

Part number	CY7C1302CV25
Manufacturer	Cypress (now Infineon)
File Size	318.27 KB
Description	9-Mbit Burst of Two Pipelined SRAMs
Datasheet	CY7C1302CV25_CypressSemiconductor.pdf

The CY7C1302CV25 is a 2.5V Synchronous Pipelined SRAM equipped with QDR™ architecture.

QDR architecture consists of two separate ports to access the memory array.

The Read port has dedicated data outputs to support Read operations and the Write Port has dedicated data inputs to support Write operations.

Separate independent Read and Write data ports.
Supports concurrent transactions.
167-MHz clock for high bandwidth.
2.5 ns clock-to-Valid access time.
2-word burst on all accesses.
Double Data Rate (DDR) interfaces on both Read and Write ports (data transferred at 333 MHz) @ 167 MHz.
Two input clocks (K and K) for precise DDR timing.
SRAM uses rising edges only.
Two output clocks (C and C) account for clock skew an.

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