CY7C1325 - 256K x 18 Synchronous 3.3V Cache RAM

Cypress (now Infineon)

Datasheet Details

The CY7C1325 is a 3.3V, 256K by 18 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic.

Maximum access delay from clock rise is 7.5 ns (117-MHz version).

A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access.

www.DataSheet4U.com CY7C1325 256K x 18 Synchronous 3.3V Cache.

Supports 117-MHz microprocessor cache systems with zero wait states.
256K by 18 common I/O.
Fast clock-to-output times.
7.5 ns (117-MHz version).
Two-bit wrap-around counter supporting either interleaved or linear burst sequence.
Separate processor and controller address strobes provides direct interface with the processor and external cache controller.
Synchronous self-timed write.
Asynchronous output enable.
I/Os.

Part Number	Description
CY7C1325G	4-Mbit (256K 횞 18) Flow-Through Sync SRAM
CY7C1325H	4-Mbit Flow-Through Sync SRAM
CY7C132	2K x 8 Dual-Port Static RAM
CY7C1320AV18	18-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1320BV18	18-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1320CV18	(CY7C1xxxCV18) 18-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1320JV18	18-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1320KV18	18-Mbit DDR II SRAM Two-Word Burst Architecture
CY7C1321BV18	1.8V Synchronous Pipelined SRAM
CY7C1321KV18	18-Mbit DDR II SRAM Four-Word Burst Architecture