CY7C1329
Features
- Supports 133-MHz bus for Pentium® and Power PC™ operations with zero wait states
- Fully registered inputs and outputs for pipelined operation
- 64K x 32 mon I/O architecture
- Single 3.3V power supply
- Fast clock-to-output times
- 4.2 ns (for 133-MHz device)
- 5.5 ns (for 100-MHz device)
- 7.0 ns (for 75-MHz device
- User-selectable burst counter supporting Intel® Pentium interleaved or linear burst sequences
- Separate processor and controller address strobes
- Synchronous self-timed writes
- Asynchronous output enable
- JEDEC-standard 100 TQFP pinout
- “ZZ” Sleep Mode option and Stop Clock option All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. Maximum access delay from the clock rise is 4.2 ns (133-MHz device). The CY7C1329 supports either the interleaved burst sequence used by the Intel Pentium processor or a linear burst sequence...
