CY7C1329H Datasheet 2-mbit Pipelined Sync Sram

Manufacturer: Cypress (now Infineon)

Overview: CY7C1329H 2-Mbit (64 K × 32) Pipelined Sync SRAM 2-Mbit (64 K × 32) Pipelined Sync.

Datasheet Details

Part number	CY7C1329H
Manufacturer	Cypress (now Infineon)
File Size	435.93 KB
Description	2-Mbit Pipelined Sync SRAM
Datasheet	CY7C1329H-CypressSemiconductor.pdf

The CY7C1329H SRAM integrates 64 K × 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation.

All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK).

The synchronous inputs include all add

Registered inputs and outputs for pipelined operation.
64 K × 32 common I/O architecture.
3.3 V core power supply.
2.5 V/3.3 V I/O operation.
Fast clock-to-output times.
4.0 ns (for 133-MHz device).
Provide high-performance 3-1-1-1 access rate.
User-selectable burst counter supporting Intel Pentium® interleaved or linear burst sequences.
Separate processor and controller address strobes.
Synchronous self-timed write.
Asynchronous output e.

Part Number	Description
CY7C1329	64K x 32 Synchronous-Pipelined Cache RAM
CY7C132	2K x 8 Dual-Port Static RAM
CY7C1320AV18	18-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1320BV18	18-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1320CV18	(CY7C1xxxCV18) 18-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1320JV18	18-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1320KV18	18-Mbit DDR II SRAM Two-Word Burst Architecture
CY7C1321BV18	1.8V Synchronous Pipelined SRAM
CY7C1321KV18	18-Mbit DDR II SRAM Four-Word Burst Architecture
CY7C1323BV25	18-Mbit 4-Word Burst SRAM