CY7C1321KV18 - 18-Mbit DDR II SRAM Four-Word Burst Architecture

This page provides the datasheet information for the CY7C1321KV18, a member of the CY7C1319KV18 18-Mbit DDR II SRAM Four-Word Burst Architecture family.

Product Overview

Cypress Semiconductor

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Datasheet Details

Part number	CY7C1321KV18
Manufacturer	Cypress Semiconductor
File Size	816.04 KB
Description	18-Mbit DDR II SRAM Four-Word Burst Architecture
Datasheet	CY7C1321KV18 Datasheet
Additional preview pages of the CY7C1321KV18 datasheet.

CY7C1321KV18 Product details

Description

CY7C1319KV18 and CY7C1321KV18 are 1.8 V Synchronous Pipelined SRAMs equipped with DDR II architecture.

The DDR II consists of an SRAM core with advanced synchronous peripheral circuitry and a two-bit burst counter.

Features

18-Mbit density (1M × 18, 512K × 36).
333-MHz clock for high bandwidth.
Four-word burst for reducing address bus frequency.
Double data rate (DDR) interfaces (data transferred at 666 MHz) at 333 MHz.
Two input clocks (K and K) for precise DDR timing.
SRAM uses rising edges only.
Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches.
Echo clocks (CQ and CQ) simplify data capture in high speed systems.
Synchronous.

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Other Datasheets by Cypress Semiconductor

CY7C1321BV18 - 1.8V Synchronous Pipelined SRAM
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Published: Mar 14, 2017 |